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Nanowire transistors (NW Tr.) are very promising for ultralow-power LSI [1–3]. However, Ion of reported 10nm-size NW Tr., essential for 10nm-Lg scaling, is relatively low due to large parasitic resistance (RSD) and immature performance boosters. Also, dynamic power control using substrate bias (Vsub) and circuit performance under low-Vdd operation have not been sufficiently explored yet in NW Tr.
An ultra-low voltage performance of nanowire-transistors-based CMOS circuits is investigated using the Spice model parameters. All Spice model parameters of BSIM4 are extracted from measurement data of nanowire transistors fabricated on 300 mm SOI wafer. The delay time and the power consumption of NW-Tr.-based and bulk-Tr.-based CMOS circuits are examined. The operation voltage of NW-Tr.-based inverter...
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