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We proposed a novel pre-bond functional test architecture for core-level partitioned 3D SoCs. In this test architecture, a new test access mechanism is built by probing functional Through Silicon Vias (TSVs) and by linking functional TSVs to all pins of IP cores under test. In order to reduce the Design-for-Test (DfT) cost, we propose a novel scheme to share the functional TSVs among pins of IP cores...
Testing through-silicon-vias (TSVs) is challenging largely due to the dimension gap between the TSVs and the probe needles. This paper proposes a low-cost and efficient test and diagnosis scheme without extra design for test structure or special probe technologies. A test probe head with current technology is in use, contacting multiple TSVs simultaneously. We propose an efficient binary search-based...
TSVs can be fabricated with pitch of only tens of μm, and smaller. They can be densely distributed as inter-die interconnect in 3D ICs. However, the huge mismatch between the probe technology, such as the pitch of probe head and the capacity of probe card, and the TSV fabrication technology leads to an insufficient probe on TSV tips. In this paper, we present a novel TSV probing technique that can...
Three-dimensional (3D) integration based on through-silicon-vias (TSVs) is rapidly gaining traction for industry adoption. However, manufacturing processes for TSVs have been shown to introduce new failure mechanisms. In particular, thermo-mechanical stress and electromigration introduce reliability threats for TSVs, e.g., voids and interfacial cracks, which can lead to hard-to-predict timing errors...
Three-dimensional (3D) integrated circuits (ICs) that stack multiple dies vertically using through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The shift towards volume production of 3D-stacked ICs, however, requires their manufacturing yield to be commercially viable. Various techniques have been presented in the literature to address this important problem, including...
3D-stacked ICs that employ through-silicon vias (TSVs) to connect multiple dies vertically have gained wide-spread interest in the semiconductor industry. In order to be commercially viable, the assembly yield for 3D-stacked ICs must be as high as possible, requiring TSVs to be reparable. Existing techniques typically assume TSV faults to be uniformly distributed and use neighboring TSVs to repair...
Three-dimensional (3D) stacking using through silicon vias (TSVs) is a promising solution to provide low-latency and high-bandwidth DRAM access from microprocessors. The large number of TSVs implemented in 3D DRAM circuits, however, are prone to open defects and coupling noises, leading to new test challenges. Through extensive simulation studies, this paper models the faulty behavior of TSV open...
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