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Toward integrating memristors in CMOS-based designs flexible prototyping environments are necessary. However, research in digital memristive systems so far lacks an adequate testing platform for real world devices. To achieve better handson experience, we developed a flexible FPGA-based solution which allows to link memristors with arbitrary compute units such as MIPS, ARM processor cores or own custom...
In this paper, we present our solution to simulate home automation networks on a functional level in our research project on self-organizing home automation network nodes. We simulate the nodes with our hardware-software co-simulator, based on the virtual machine QEMU and the SystemC hardware simulator. The Virtual Distributed Ethernet suite is used to simulate several hardware-software co-simulators...
The paper proposes an architecture for a multiplier-adder network that can be used for the design of a digital neuron cell. The core of the multiplier is based on a hybrid memristor network, in which digital CMOS logic is combined with multi-stable storing memristor devices. The multi-bit storing feature of memristors is favoured since it simplifies the realisation of ternary data. Using such a ternary...
The advancing automation of the industrial production requires faster and more efficient programmable logic controllers. Today's controller architectures based on specialized processors to execute the STL application are at their limits. For any further improvement the architecture of these processors needs to evolve from single core in order execution to a multicore out of order architecture. This...
We present a fine-grain parallel processor chip which can be embedded in very compact machine vision systems, e.g. in 3d stacked die assemblies. Smart and fast vision systems are frequently required in industrial environments to automatically detect and inspect objects, e.g. on an assembly line. The chip die has a size of 25 mm2 and is manufactured using a 0.18 um CMOS technology. The chip processes...
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