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We present gate all around strained Si (sSi) nanowire array TFETs with high ION (64μA/μm at VDD=1.0V). Pulsed I-V measurements provide small SS and record I60 of 1×10−2μA/μm at 300K due to the suppression of trap assisted tunneling (TAT). Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and ION. Transient analysis of complementary TFET inverters demonstrates...
In this work, we explore the potential of Kelvin Force Microscopy (KFM) measurements to investigate the lateral charge transport in SiN layers with two different compositions (standard, std, and Silicon rich, Si-rich). The dynamics of the lateral spread of the trapped charge is analyzed with the help of three dimensional numerical device simulations.
In this work a quasi-analytical physical model for the accurate prediction of the potential of GAA nanowire transistors with an arbitrary regular polygon as a cross section is developed. Two case studies concerning triangular and square cross-sections are particularly investigated and analyzed. The model is then extended to the transport direction; general expressions for the natural length are derived...
In this paper, two Monte-Carlo simulators implementing different models of the influence of carrier quantization on the electrostatics and transport are applied to sub-100nm double-gate SOI devices. To this purpose a new stable and efficient scheme to implement the contacts in the simulation of DG SOI devices is introduced first. Then, results in terms of drain current and microscopic quantities are...
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