Search results for: Yuandi Surya
chapter
A clock skew-compensation and/or duty-cycle correction circuit (CSADC) is indispensably required to maximize the performance of synchronous double edge triggered systems. Most conventional CSADCs adopted a cascade structure that inherits a lower performance property so as to slower the locking procedure, meanwhile the dual loop design results in more power consumption and design complexity. A range...
chapter
A clock skew-compensation and/or duty-cycle-correction circuit (CSADC) is indispensably required to maximize the performance of a synchronous double edge clocking system. Most conventional CSADCs adopted a cascade structure that inherits a lower performance property so as to slower the locking procedure, meanwhile the dual loop design results in more design complexity. A compact delay-recycled CSADC...
