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In this paper, a UART design is proposed. The design has an auto-tuning baud rate generator. For achieving the speed matching of the processor and UART interface, it takes asynchronous FIFOs as buffers to realize data exchange between UART and external devices. The whole design is functionally verified using ModelSim SE 6.0, and synthesized and optimized by Synplicity's Synplify Premier 9.6.2.
Clustered voltage scaling (CVS) systems is an efficient power reduction technique. One of the design challenges in CVS is the efficient level-converting flip-flop (LCFF) with less overhead in power and delay. In this paper, a level converting flip-flop based pass-transisor logic (LCFFBPT) and a static level converting flip-flop (SLCFF) are proposed, respectively. In addition, the two level-converting...
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