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The power integrity characterization of a high-capacity, compute-server memory system operating at 4.8Gbps-per-link is presented. The design robustness of the low-swing, single-ended signaling is verified as the system has excellent immunity to the noise from simultaneously switching outputs (SSO) and a low power-supply-induced jitter (PSIJ) at the primary chip-package resonance frequency.
Accurate analysis of link performance including deterministic and random effects as well as advanced signal conditioning schemes is crucial in modern high-speed I/O design. In recent years, statistical link performance tools such as LinkLab and StatEye are introduced to efficiently analyze the overall link performance with both deterministic and random noise. The statistical-domain analysis has limitations...
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