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A 58-60.4GHz frequency synthesizer is implemented in a 90nm CMOS process. A VCO with a distributed-LC tank and a current-reuse frequency divider are used. For 60.4GHz, the measured phase noise at 1 MHz and 2MHz offset is -85.1dBc/Hz and -95dBc/Hz, respectively. Including the buffers, the chip consumes 80mW from a 1.2V supply.
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