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A circuit for automatic detection of action potentials (spikes) in neural recording devices is presented. This circuit, designed to operate in discrete time, provides an analogue threshold level based on standard deviation of the analogue samples of the input neural signal. Functionality of the circuit was tested for normal prerecorded neural signals as the input. To examine whether the spike detection...
This paper describes an efficient structure of apseudo-differential current starved delay element that is used in a four stages delay line targeted for analog/mixed Delay-Locked-Loops. The designed circuit has been simulated in ADS software, using TSMC 0.18 um CMOS process at 1.5V supply voltage. Body feed technique is used to widen applicable range of control voltage. The linearity of circuit is,...
This paper describes an efficient structure of a pseudo-differential current starved delay element that is used in a four stages delay line targeted for analog/mixed Delay-Locked-Loops. The designed circuit has been simulated in ADS software, using TSMC 0.18 um CMOS process at 1.5V supply voltage. Body feed technique is used to widen applicable range of control voltage. The linearity of circuit is,...
A novel analog-to-digital converter (ADC) architecture, named domino architecture, is introduced. The proposed idea can be taken as the continuous-time counterpart of SAR ADCs, and at the same time it resembles a series version of flash ADCs being implemented with much less circuit complexity and chip area. The basic idea is then pipelined in order to speed up the conversion process, leading in a...
An analog spike detector circuit is presented, which adaptively generates a threshold level for spike detection based on hard-thresholding. Operation of the circuit was tested not only with a neural signal obtained from real in-vivo recording from a live animal, but also with a large sinusoidal baseline variation intentionally added to examine the capability of the circuit to track baseline variations...
An implantable neural recording front-end has been designed in two versions. The first is a multi-channel signal-conditioning ASIC for use with any neural recording probe technology. This ASIC was implemented in a commercial 0.5??m CMOS process, includes 16 parallel amplifier channels, and measures 2.3mm2. The amplifiers have a gain of 59.5dB, a high cutoff frequency at 9.1kHz and consume 75??W per...
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