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In this paper, we report for the first time electrical performances of high hole mobility pMOSFETs with high-k/metal gate using ultra-thin GeOI wafers as templates obtained by the Ge condensation technique. It is concluded that the results coupled with a localized Ge condensation technique, open the way to planar SOI-nMOSFET/GeOI-pMOSFET co-integration.
For the first time, we integrated and compared the electrical performances of high-K / metal embedded gate in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO2, TiN/SiO2 or N+ poly-Si/SiO2 were compared to a planar reference. In particular we investigated electron and hole mobility behaviours (300 K down to 20 K)...
Very high Ge content SiGe virtual substrates (50% les [Ge] les 70%) can serve as templates for the growth of compressively strained Ge (c-Ge) / t-Si dual channels, with impressive hole mobility enhancements (up to 10) over bulk Si based in M. L. Lee and E. A. Fitzgerald (2003) and O. Weber et al. (2005). SiGe virtual substrates graded all the way up to pure Ge according to M. T. Currie et al. (1998)...
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