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A systematic design method is applied to perform the loop stability and noise analyses for a type-II 3rd-order charge pump PLL. The measured phase noise has shown that the phase noise breakdown simulation can accurately evaluate the PLL performance. The designed PLL outputs a clock at more than 10 GHz for an on-chip SerDes system. The design consideration and trade-off are detailed. The PLL is designed...
A 4-level pulse amplitude modulation (PAM-4) silicon photonic transmitter targeting operation at 25 Gb/s is designed using an electrical-photonic co-design methodology. The prototype consists of an electrical circuit and a photonics circuit, which were designed in 130 nm IBM SiGe BiCMOS process and 130nm IME SOI CMOS process, respectively. Then the two parts will be interfaced via side-by-side wire...
A systematic design method is applied to study and analyze the loop stability and phase noise of a type-II 3rd-order charge pump PLL. The designed PLL outputs at 12.5 GHz, which is intended to provide a clock for a silicon photonic transmitter prototype. The charge pump current and loop filter resistor are made tunable to cover process and temperature variations. The PLL is designed in a 130 nm SiGe...
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