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In current systems-on-chip (SoC) designs, managing peak temperature is critical to ensure operation without failure. Our novel communication architecture based thermal management (CBTM) scheme manages thermal behavior of components by delaying the execution of chosen IP-blocks or components by regulating the flow of data over the on-chip communication bus. This temperature aware traffic flow over...
Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system's power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage Vdd and temperature on memory performance and their interrelationships. We propose a Temperature- and Reliability- Aware Memory Design (TRAM) approach which...
Increased operating temperatures of chips have aggravated leakage and reliability issues, both of which are adversely affected by high temperature. Due to thermal diffusion among IP-blocks and the interdependence of temperature and leakage power, we observe that the floorplan has an impact on both the temperatures and the leakage of the IP-blocks in a system on chip (SoC). An increase in temperature...
Summary form only given. Improvements in the speed and the size of chips due to process scaling come with the penalties of increased power densities and higher operating temperatures. Higher temperature not only poses a risk of thermal runaway of the chips but also increases leakage-power dissipation and reduces interconnect lifetime. Furthermore, the floorplan of a System-on-a-Chip (SoC) has a significant...
Voltage scaling is one of the knobs that is used today to control both static and the active power for SoCs. The SoC core supply voltage is scaled adaptively based on the performance needs. But it is also required to maintain the external electrical chip interface protocol, which may run at a different voltage level. The chip interfaces need to operate reliably under adaptively scaling core voltage...
Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage power, we observe that the floorplan has an impact on both the temperatures and the leakage of the IP-blocks in a system on chip (SoC). Hence, in this paper we propose a novel system level leakage aware floorplanner (LEAF) which optimizes...
Multi-million gate system-on-chip (SoC) designs increasingly rely on intellectual property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP blocks has risen thus leading to possible thermal runaway. In IP-based design there has been a disconnect between system level design and physical level steps such as floorplanning which can lead to failures in manufactured...
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