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Long error detection latency, the time elapsed between the occurrence of an error caused by a bug and its manifestation as a system-level failure, is a major challenge in post-silicon validation of robust systems. In this paper, we present a new technique called Quick Error Detection (QED), which transforms existing post-silicon validation tests into new validation tests that significantly reduce...
Traditional architecture design approaches hide hardware uncertainties from the software stack through over-design, which is often expensive in terms of power consumption. The recently proposed quantitative alternative of stochastic computing requires circuits and processors to be correct only probabilistically and use less power. In this paper, we present the first step towards a theory of stochastic...
Robust system design ensures that future systems continue to meet user expectations despite rising levels of underlying disturbances. This paper discusses two essential aspects of robust system design: 1. Effective post-silicon validation, despite staggering complexity of future systems, using a new technique called Instruction Footprint Recording and Analysis (IFRA). 2. Cost-effective design of systems...
IFRA overcomes challenges associated with an expensive step in post-silicon validation of processors - pinpointing the bug location and the instruction sequence that exposes the bug from a system failure. On-chip recorders collect instruction footprints (information about flows of instructions, and what the instructions did as they passed through various design blocks) during the normal operation...
The objective of IFRA, instruction footprint recording and analysis, is to overcome the challenges associated with a very expensive step in post-silicon validation of processors - bug localization in a system setup. IFRA consists of special design and analysis techniques required to bridge a major gap between system-level and circuit-level debug. Special hardware recorders, called footprint recording...
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