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In this study, we propose a new technology to fabricate pseudo tri-gate vertical (PTGV) MOSFETs without p-n junctions, named junctionless PTGVMOS (JPTGV). According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ~ 60mV/dec, Ion/Ioff ~ 1010, and low interface trap density are all achieved. The device without p-n junctions provides an easier way for...
A new planar-type body-connected FinFET structure produced by the isolation-last self-align process is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. The new process step first defines the gate region and then the active region, thus it can achieve fully self-alignment undoubtedly. Besides, due to the isolation-last process (ILP), an additional body region (ABR)...
A new STI-type FinFET structure with its body region been connected is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. From the simulation results, the STI-type FinFET shows that the short-channel effects (SCEs) and the off-state leakage current are proved to be reduced because the threshold voltage (VTH) roll-off and the drain-induced barrier lowering (DIBL)...
In this work, a novel device called dual-channel body-tied (DCBT) MOSFET is proposed. According to numerical simulations, the DCBT MOSFET can reduce the lattice temperature about 51.6% in top and 53.8% in bottom channel, respectively, while maintain the desirable short-channel characteristics, compared with the conventional non-body-tied DC structure.
An ultimate n-shaped source/drain (π-S/D) metal-oxide semiconductor (MOS) transistor is proposed in this paper. The method used to fabricate the proposed π-S/D transistor is based on both the classical and modern techniques (such as, Si-SiGe epitaxial growth, selective SiGe removal, etc.) that can be controllable and repeatable. Also, a new and simple process without the need of an additional mask...
This paper is to investigate the novel features of a Local Oxidation of silicon multi-tie body polycrystalline silicon thin-film transistor (LOCOS MTB poly-Si TFT) by using numerical simulations. Based on the results, our proposed TFT have improved reliability due to the presence of the LOCOS MTB scheme. Although a multi-body-tied scheme is not compatible in current TFT process, it is believed that...
This paper presents a non-classical architecture called the bottom gate MOSFET with source/drain tie (S/D-tied BG) to achieve enhanced device reliability. According to the 2-D numerical simulation, the proposed structure can effectively reduce the effects of self-heating because of its source/drain-tied scheme, resulting in improved thermal stability. In addition, S/D-tied BG MOSFET not only diminishes...
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