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We present a reliability analysis of a new vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM applications. The proposed 1T-DRAM device can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved by about 95% when compared to the planer bMPI 1T-DRAM. Owing to the double-gate structure,...
In this work, a novel device called dual-channel body-tied (DCBT) MOSFET is proposed. According to numerical simulations, the DCBT MOSFET can reduce the lattice temperature about 51.6% in top and 53.8% in bottom channel, respectively, while maintain the desirable short-channel characteristics, compared with the conventional non-body-tied DC structure.
This paper is to investigate the novel features of a Local Oxidation of silicon multi-tie body polycrystalline silicon thin-film transistor (LOCOS MTB poly-Si TFT) by using numerical simulations. Based on the results, our proposed TFT have improved reliability due to the presence of the LOCOS MTB scheme. Although a multi-body-tied scheme is not compatible in current TFT process, it is believed that...
In this paper, we examine the current-voltage (IV) and capacitance-voltage (CV) characteristics of self-aligned (SA), planar block oxide (BO) metal-oxide semiconductor field-effect transistors (MOSFETs) using technology computer-aided design (TCAD) tools. For the first time, a comparison of the different types of BO MOSFETs, such as fully depleted silicon-on-insulator (FDSOI) FET with BO (bFDSOI),...
To improve the bSPIFET, the SA-bSPIFET which used self-aligned process had been proposed. However there are many characteristics of bSPIFET not yet be studied. This paper focuses on the misalignment of gate shift (GS) in a 30 nm bSPIFET. Based on 2D simulation, the misalignment of GS will influence the electrical characteristics causing the degradation of the short channel behaviour and the stability...
In this paper, for the first time, a novel devise-architecture namely multi-source/drain SOI MOSFET is proposed and compared with a conventional SOI MOSFET. According to the simulation result, our proposed transistor not only maintains the desirable short channel behaviour, but also enhances the on/off current ratio due to the multi-source/drain scheme.
This paper investigates the device behaviours of a pseudo tri-gate ultra-thin-channel vertical MOSFET with source/drain tie. For comparison two transistors are designed. According to the 2D simulation, our proposed structure can effectively enhance the drain current and the thermal stability, mainly due to the ultrathin channel (Tsi = 10 nm). The fabricated device have very low subthreshold swing...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
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