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We present a pipelined 32-bit Instruction Set Extension (ISE) for complex valued floating point operations. The ISE was implemented in the NIOS II processor, and the constraint on the number of inputs and outputs of the register bank was overcome by distributing the reads and writes of the instruction over several cycles. The hardware size was reduced by sharing hardware between instructions. The...
As increasing the clock frequency leads to unmanageable heat and power dissipation the search is on for another way to get more power efficient and faster embedded systems. Given that chip area is also a constraint, we investigate the addition of a custom instruction to the processor instruction set which enables the execution of an efficient complex division. The instruction we designed is a hardware...
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