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Because Moore's law is always still working and the requirement of energy-saving still exists, CPU architecture is becoming more and more complicated and developing to Many-core architecture. But many-core is incompatible with the current programming mode designed for single-core CPU. This paper proposed a Block level Hardware-based Scheduling on many-core architecture (BHS) by adding the program...
Regular expression is an important approach which is widely used in string pattern matching. And in many pragmatic applications string pattern matching is the most compute intensive task which takes majority processing time, therefore, in order to improve system efficiency many works have been done around hardware implementation of regular expression matching. However, the traditional design approaches...
In order to design a faster CPU, it is becoming more and more complex on the CPU architecture. But many-core is incompatible with the current programming mode designed for single-core CPU. This paper proposes a Block level Hardware-based Scheduling (BHS) on many-core architecture. The two main features are: First, design and implement a block-based hardware scheduler to reduce the overhead of threads,...
With the development of semi-conductor industry, more transistors can be integrated onto a single chip. But the software programming model cannot fit the parallelism requirement of CMP (Chip Multi Processor) based architecture. The communication between different cores becomes a very serious problem, and it made bad effectiveness on performance. This paper proposes an approach called API (Architecture...
Reconfigurable computing based on FPGAs (Field Programmable Gate Arrays) has been a promising solution to improve the performance with high flexibility. However, the physical capacity limitation of FPGAs prevents its wide adoption in real world. In this paper, a homogeneous NoC-based FPGA architecture is proposed, in which reconfigurable and I/O resources are interconnected via NoC so that reconfigurable...
Executing sequential program on multi-core is crucial for accommodating instruction level parallelism (ILP) in chip multiprocessor (CMP) architecture. One widely used method of steering instructions across cores is based on dependency. However, this method requires a sophisticated steering mechanism and brings much hardware complexity and area overhead. This paper presents the Global Register Alias...
Network on Chip (NoC) is proposed as a promising solution for processors with many cores integrated onto a single chip. The main advantages of NoC are favorable scalability and high bandwidth for on-chip cores and communications. However, OS designed for NoC have not been fully researched to date. Because the microkernel operating system is composed of modules, such architecture is suitable to execute...
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