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This paper presents a high linearity and low power up-conversion mixer at 3.0-5.0 GHz for UWB applications in TSMC 0.18-μm CMOS technology. The design based on Gilbert-cell active double-balanced mixer using a capacitor located in parallel with the intrinsic gate-source capacitor of a transconductance stage for high linearity. The source degeneration inductors helps to improve linearity...
Typical and proposed recycling folded cascade (RFC) amplifier have been designed in TSMC 0.18 μm. Simulated and measured results are compared. Proposed RFC demonstrate an enhancement on DC gain by 5 dB almost for the same power consumption and bandwidth. Moreover, it realized less input referred noise than typical. Split-length devices (SLD) method is applied on proposed (RFC) to create...
This paper presents a comparison between bipolar and NMOS transistor to get high linearity amplifier. Using bipolar transistor, the amplifier has high linearity, and it does not sensitive to component variations. High linear amplifier using bipolar transistor has been designed and was fabricated using TSMC 0.18 um CMOS 1P6M process. The high linearity amplifier exhibits measurements results as 10...
This paper presents a simple architecture for 8-bit digital controlled oscillator (DCO) on 3-stages ring topology in TSMC 0.35 mum CMOS technology. A new schematic of tristate inverter is also proposed. The proposed tristate inverter has higher switching speed and low power consumption as compared to conventional one. The control digit changes the driving current that provides large tuning range from...
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