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This paper presents the design and implementation of a quadrature voltage-controlled ring oscillator with the improved figure of merit (FOM) using the four single-ended inverter topology. A new topology to prevent the latch-up in single ended ring oscillators is proposed. The design is implemented in 0.18 μm CMOS technology and the measurement results show a FOM of -163.8 dBc/Hz with the phase noise...
This paper presents a low phase noise quadrature ring oscillator with new start-up circuit. The oscillator architecture is two-stage differential ring with additional pair of transition-assistance inverters. The circuit was implemented in 0.18 mum CMOS technology and the measured tuning range of the prototype device is from 1.7 GHz to 5.5 GHz and figure of merit (FOM) is -162 dB. The proposed area...
This paper presents a simple architecture for 8-bit digital controlled oscillator (DCO) on 3-stages ring topology in TSMC 0.18 um CMOS technology. A new schematic of tristate inverter is also proposed. The proposed tristate inverter has higher switching speed and low power consumption as compared to conventional one. The control digit changes the driving current that provides large tuning range from...
This paper presents a simple architecture for 8-bit digital controlled oscillator (DCO) on 3-stages ring topology in TSMC 0.35 mum CMOS technology. A new schematic of tristate inverter is also proposed. The proposed tristate inverter has higher switching speed and low power consumption as compared to conventional one. The control digit changes the driving current that provides large tuning range from...
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