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Folding and interpolating A/D converters have been shown to be an effective means of digitization of high bandwidth signals at intermediate resolution. The paper focuses on design of low power 5-bit folding & interpolating ADC. The folding amplifier can be used to produce more than one zero-crossing point to reduce required number of comparators. The converter is designed using novel low voltage,...
Because of increased design complexity and advanced fabrication technologies, the number of tests and corresponding data volume increases rapidly. As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed in past. Run length coding is one of the most familiar coding methodologies for compression...
Test data compression is a basic necessity for today's test methodology with reference to test cost and test time. This paper presents a compression/decompression scheme based on frequency dependant bit appending of test vector used with statistical codes. In the proposed scheme, the emphasis is not only on data compression but it aims the data compression with a smaller amount of silicon area overhead...
The folding and interpolating ADC has speed advantage similar to flash ADC with reduced complexity. The folding amplifier can be used to produce more than one zero-crossing point to reduce required number of comparators. This paper presents simple low voltage, low power folding amplifier with folding factor=4 for folding and interpolating ADC. The design is implemented using 0.13 um technology at...
As a result of the emergence of new fabrication technologies and design complexities, standard stuck-at scan tests are no longer sufficient. The number of tests and corresponding data volume increase with each new fabrication process technology. The demand goes to well beyond 100X tester cycle reduction considering new fault models. The test data compression has been an emerging need of VLSI field...
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