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Future CMOS technology generations require novel materials in the front end of device fabrication to overcome physical limits of the classical silicon/silicon dioxide based system and to keep control over channel charge: 1.) High-k dielectrics and metal gate electrodes enable scaling of the equivalent oxide thickness maintaining reasonable gate leakage currents. 2.) Thin, fully depleted silicon on...
A FUSI NiSi metal gate technology is used to investigate the scaling potential of high-k epitaxial gadolinium oxide (Gd2O3) down to 0.6 nm equivalent oxide thickness. Thermally stable gate stacks have been realized by TiN electrodes on gadolinium silicate. Work function tuning of mid gap electrodes is achieved by insertion of ultrathin AlN buffer layers. Initial results based on sputtered buffer layers...
In this work we present a gate-first process platform for device integration of gadolinium (Gd) based high-k dielectrics and metal gate electrodes. Epitaxial Gd2O3 and GdSiO high-k layers have been integrated with titanium nitride (TiN) gates. Thermal stability of the gate stacks is investigated in detail. Especially the metal inserted polysilicon approach using TiN enables high temperature processing.
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