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Quantum cellular automata (QCA) represents an emerging technology at the nanotechnology level. Because of high speed, nanoscale size and ultra low power nature of QCA, cryptography can be an interesting application of QCA technology. QCA implementation of the Serpent block cipher is discussed in this paper. The basic modules of Serpent are implemented using QCA cells. It can be obviously seen that...
This paper describes the non-linear averaged value models for different configurations of an 18-pulse rectifier. The models allow rectifier and drive system interactions to be examined analytically, or through rapid simulation. The models are validated by comparison with a detailed circuit simulation.
This paper specifies Alamout, a new hardware oriented synchronous stream cipher with an associated authentication mechanism. The design is small in hardware and it targets environments with limited resources. Alamout supports key size of 80 bits and IV size of 128 bits. The Alamout cipher has been designed to produce keystream with guaranteed randomness properties. Simulation with ENT randomness test...
The principle, configuration, and the special features of a stable platform digital controller are presented in this paper. The main goal of this paper is replacing an analog controller with its awaiting digital one. This has been done using TMS320LF2402 digital signal processor which offers the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance...
Frequency analysis using the discrete cosine transforms (DCT) is an obvious choice for digital signal and image processing domain. This paper describes the implementation of 2D-DCT processor for the synchronous design in a Xilinx VertexIV FPGA device. The DCT core architecture is based on the distributed arithmetic. The total dynamic power of the processor is 371 mW, in an operating frequency of 118...
Jitter transfer function of a clock and data recovery circuit (CDR) must satisfy difficult specifications versus of loop bandwidth and jitter peaking. This paper describes the method of setting poles and zero in third order CDR circuit to keep jitter peaking below a certain value required by specific optical standards. The results are validated by MATLAB simulations for a 10 Gb I s clock and data...
Frequency analysis using the DFT, the DHT, the DCT or the DST is an obvious choice for signal processing domain. This paper describes the implementation of a DXT coprocessor of transform length '8' for the synchronous design in a 0.22 LM Flash-based FPGA device (ACTEL). The total dynamic power of 359.24 mW, with an operating frequency of 50 MHz and an operating voltage of 2.5 V is achieved. The paper...
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