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In this paper, we propose a dynamic voltage scaling (DVS) policy for a fully asynchronous NoC suitable for low-power yet high-performance architectures. The DVS policy is a FIFO-adaptive DVS, which uses two FIFO threshold levels for decision. It judiciously adjusts switch voltage among only three voltage modes. The introduced architecture is simulated in 90 nm CMOS technology with accurate Spice simulations...
In this paper, we present a fast yet accurate semi-analytical model for the I-V and C-V characteristics of nanoscale undoped symmetric double gate (DG) MOSFETs. The model employs a simple parabolic potential approximation for the body potential in the coordinate normal to the interfaces in the all regions of operation. To include quantum effects in the model, the Schrodinger's equation is analytically...
As nanotechnology scales down, the reliability issues are becoming more crucial, especially for Network-on-Chip (NoC) which must provide the communication requirements of Multi-Processor System-on-Chip (MP-SoC) even in presence of faults. In this paper we present a low cost faulty-link-tolerant routing algorithm through dynamic reconfiguration when the regular mesh topology is altered by faulty links...
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