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A low-power, high-performance 4-way 32-bit vector processor is developed for handheld 3D graphics systems. It contains a floating-point unified matrix, vector, and elementary function unit. By utilizing the logarithmic arithmetic, the unit achieves single-cycle throughput for all these operations except for the matrix-vector multiplication with 2-cycle throughput. The processor featured by this function...
A 3D graphics processor fabricated using 0.18mum 6M CMOS contains 1.57M transistors and 29kB SRAM in a core size of 17.2mm2. The vertex shader utilizes a logarithmic number system for 141 Mvertices/s and the 3 power domains are controlled separately by dynamic voltage and frequency scaling for 52.4mW at 60fps.
A low-power, area-efficient 4-way 32-bit unified vector and transcendental function unit has been developed for programmable shaders for handheld 3-D graphics systems. It adopts the logarithmic number system (LNS) at the arithmetic core for the small-size, low-power unification and single cycle throughput with maximum 4-cycle latency of various vector and transcendental functions. A novel logarithmic...
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