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Barrier engineered charge-trapping NAND flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multi-layer barrier is derived using WKB approximation. The rigorously derived analytical form is valid for both electron and hole tunneling, as well as for any barrier composition. With this, the time evolution...
Incremental-step-pulse programming (ISPP) is a key enabler for achieving tight VT distribution for MLC NAND Flash. The ISPP characteristics for BE-SONOS NAND Flash are studied extensively in this work. Experimentally we find that the ISPP slope is very close to 1 for BE-SONOS capacitors for a wide range of EOT and O1 variations. A theoretical model is developed to prove that ISPP slope~1 is a universal...
Unlike the floating gate Flash device, charge-trapping (CT) devices store charges locally and are thus profoundly affected by non-uniform injection effect. The characteristics of a CT device are dominated by the local minimum-Vt region along the channel width. We have analyzed various STI structures including raised-STI, recessed-STI, and near-planar structures, and found that the program/erase characteristics...
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