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System on chip is a system consists of a number of intellectual property cores (IP cores) which are connected together utilizing electrical bus technology. When the number of IP cores increases, network on chip (NoC) architectures with regular topology instead of traditional bus based architecture are used. Mapping of IP cores on a given architecture is one of the three important topics of NOC design...
The NoC paradigm is one, if not only one, fit to enable the integration of an exceedingly large number of computational, logical and storage blocks in a single chip. The paper presents a novel technique called CGMAP,which finds a mapping of the vertices of a task graph to the tiles of a mesh based NoCarchitecture, with an objective of improving the Quality of Service (QoS) in networks-on-chip.The...
In this paper we present the basic ideas behind the development of our novel ring based network-on-chip (NoC) architecture, called ldquoCoronardquo. To achieve minimum hop count, shortest path routing has been applied. Consequently, this ends in average latency reduction (averagely 45%). NS-2 tool is utilized to estimate average latency and packet drop in Corona and 2D mesh with localized and non-localized...
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