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For an all-digital phase-locked loop, the frequency range supported is often segmented, and this could cause significant jitter when the operating condition (such as the supply voltage and/or the temperature) changes. To address this issue, we present a scheme, called smooth code-jumping, that can stitch together the segmented frequency profile of a digitally controlled oscillator (DCO) into a continuous...
Multi-phase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this paper we propose a MPCG design with two major innovations: (1) We use a process calibration scheme that makes the per-phase delay (defined as the timing difference between two consecutive clock signals) highly accurate. (2) We further exploit...
We present a fully cell-based All-Digital Phase-Locked Loop (ADPLL) with almost continuous tracking range of frequency. Using TSMC 0.18μm CMOS technology, this test chip can operate from 91.6MHz to 1.173GHz with an average resolution of 2.1ps. It features a new Mirror-DCO-Based Calibration Mechanism that enables smooth code-jumping to mitigate the segmented clock-period profile problem faced by most...
In this paper, we introduce a systematic power analysis framework for SoC designs using bottom-up power modeling integrated with top-down power estimation. Four power analysis tools have been realized: (1) PowerBrick, a power characterization tool to construct power libraries for standard cell library and memory compiler, (2) PowerMixer, an RTL/gate-level power estimator for large logic design, (3)...
In this paper, we present an automatic leakage power modeling method for standard cell library as well as SRAM compiler. For this problem, there are two major challenges - (1) the high sensitivity of leakage power to the temperature (e.g., the leakage power of an inverter can be different by 19.28X when temperature rises from 25°C to 100°C in 90nm technology), and (2) the large number of models to...
In this paper, we introduce an integrated power methodology for multi-core SoC designs. It features not only a bottom-up IP-based power modeling for all kinds of IP components ranging from hardware accelerators, processors, and memory blocks, but also a top-down system-wide ESL power estimation formulation. By linking these two methods of different levels of abstraction, one can thereby easily profile...
Various logic design styles have been proposed to counteract DPA (Differential Power Analysis) attacks for secure cryptographic IC design. However, only a couple of papers addressed the automatic synthesis and optimization for these secure logic circuits. This paper attempts to identify common optimization issues in typical masking-based countermeasures. They include (1) constrained Reed-Muller (RM)...
Cryptographic embedded systems are vulnerable to differential power analysis (DPA) attacks. This paper propose a logic design style, called as pre-charge masked Reed-Muller logic (PMRML) to overcome the glitch and dissipation timing skew (DTS) problems in design of DPA-resistant cryptographic hardware. Both problems can significantly reduce the DPA-resistance. To our knowledge, the DTS problem and...
The allocation of device variables on I/O registers affects the code size and performance of an I/O device driver. This work seeks the allocation with the minimal software or hardware cost in a hardware/software codesign environment. The problems of exact minimization under constraints are formulated as zero-one integer linear programming problems. Heuristic algorithms based on iterative refinement...
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