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A time-interleaved 12-b SAR ADC, employing the proposed digital calibration with a delay-sampling technique to correct timing skew, achieves a 600-MHz sampling rate. The 600-Ms/s ADC has been fabricated in a 40-nm CMOS technology, improving SFDR from 55 dB to 71 dB for a 100-MHz input signal. The 4-way interleaved ADC achieves a 61-dB SNDR while dissipating 23 mW from a 0.9-V power supply.
A 12-bit 210-MS/s 2-channel time-interleaved analog-to-digital converter (ADC) employing a pipelined-SAR architecture for low-power and high-speed application is presented. The proposed ADC is partitioned into 3 stages with a passive residue transfer technique between the 1st and 2nd stages for power saving and active residue amplification between the 2nd and 3rd stages for noise consideration. Furthermore,...
Recent radio architectures, such as WiGig and 5G, require ADCs with bandwidth beyond 1GHz and ENOB of 6-to-8b while retaining excellent power efficiency for long battery life. Therefore, many time-interleaved SAR ADCs are used in a distributed sampling scheme, leaving the timing-skew problem to be resolved by calibration. Only a few timing-skew calibration algorithms have been reported for interleaved...
A 210 MS/s dual-channel 12-bit analog-to-digital converter (ADC) employing a pipelined successive approximation (SAR) architecture is presented. The ADC is partitioned into 3 stages with passive residue transferring between the 1st and the 2nd stages and active residue amplification between the 2nd and the 3rd stages. The ADC consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.48 dB at a...
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