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A compact model for power devices with advanced technology is developed which considers the geometry dependent potential distribution along the device explicitly. The model solves key potential nodes within the device iteratively to realize accurate modeling of the underlap, which occurs in HV\MOSFETs, as well as of the non-monotonous potential-distribution region. With use of the developed model...
The additional channel-dopant layer of normally-on MOSFETs leads to accumulation-layer current near channel surface and deeper-lying neutral-region current above the p/n junction, which dominate bias conditions above and below flat-band, respectively. The developed compact model accurately captures these currents and exploits their different bias-condition properties for efficient parameter extraction.
We present a 0.5 V 6T SRAM fabricated in a 90 nm PD-SOI technology with asymmetric MOSFET to improve the read and write margin. The design also uses a forward-body-bias technique in the bit-cell and peripheral circuits. The measured minimum operating voltage of the SRAM is 0.45 V at 25??C, which is 100 mV lower than conventional SRAM. The access time is 6.8 ns at 0.5 V.
A reliable tantalum (Ta) gate device technology, which can drastically reduce the number of process steps, has been developed. Ta gate Fully-Depleted-Silicon-On-Insulator (FDSOI) MOSFETs with 0.15 /spl mu/m gate length by low-temperature processing below 500/spl deg/C after the gate oxide formation have good on/off characteristics. Comprehensive design guidelines for Ta gate MOSFETs in the deep-submicron...
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