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In this paper, the authors demonstrate a standard cell-based circuit technique fully operational at supply voltages between 84 mV and 62 mV in standard 0.13 μm bulk CMOS depending on the area overhead invested. Supply voltage reduction is limited by the degradation of the on/off current-ratio of CMOS transistors with decreasing VDD, causing the leakage currents through the off transistors to be on...
A multiplierless structure using an 8th order band pass (BP) sigma delta (Σ△) modulator for synthesizing the intermediate frequency (IF) signal is presented in this paper. A fractional delay interpolation filter combining cascaded integrator-comb (CIC) and Lagrange filters is used before the Σ△-modulators to suppress the image caused by the time-interleaving in the IQ-paths. Closed form formulas for...
A power-efficient narrow-band tunable digital front end (DFE) for bandpass sigma-delta (ΣΔ) analog-to-digital converters is presented. The proposed architecture introduces a new system topology, splitting the down converter into two mixers and placing a cascaded integrator-comb decimation stage between the two mixers. The first mixer is a quadrature mixer that works at a quarter of the sampling frequency...
This paper introduces a novel selection criterion to choose between transposed and direct form filters for power efficient FIR polyphase decimators. Less than 5% tolerance between calculated power consumption using the proposed criterion and simulated results is observed. A combined architecture of transposed and direct form filters for power efficient FIR polyphase decimators is proposed. A decimator...
This paper introduces a state-of-the-art design of a high speed sigma delta digital to analog converter (DAC), which can be integrated into a system-on-a-chip (SOC) for different communication transceivers. The operation speed in the digital circuit is very important for accomplishing the performance which can satisfy different communication protocol specifications. This paper therefore addresses...
A novel method for approximating filter coefficients to signed-power-of-two terms is proposed yielding a significant reduction in complexity and power consumption. A Matlab toolbox named MSD-Toolbox (multi-stage decimation) was developed to design and optimize multi-stage decimation filters. The proposed design methodology was used to design an example decimation filter, which was synthesized in 0...
This paper introduces an improved method for pulse shaping filtering in a digital communication modulator. This method uses memory to store different waveform frames instead of the FIR filter coefficients. At the run time, the interpolation for pulse shaping can be directly done by retrieving these waveforms from the memory without any arithmetic operations which are needed in the conventional FIR...
This paper investigates self-timed asynchronous design techniques for subthreshold digital circuits. In this voltage range extremely high voltage-dependent delay uncertainties arise which make the use of synchronous circuits rather inefficient or their reliability doubtful. Delay-line controlled circuits face these difficulties with self-timed operation with the disadvantage of necessary timing margins...
This paper presents the implementation and power analysis of an efficient decimator architecture for cascaded sigma-delta (SigmaDelta) modulators. The recombination logic for cascaded modulators in general and a gain error correction for continuous time (CT) modulators are integrated into the first decimation stage. An appropriate filter topology is derived and synthesized in a 0.18 mum CMOS technology...
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