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In this paper we discuss timing details and performance of the ultra low voltage (ULV) logic style. The ULV logic gates can be utilized to design high speed systems operating at ultra low supply voltages. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offsets voltages are used to shift the effective threshold voltage...
This paper introduces a structure for self-refreshing multiple valued memory. The idea is to use structures having repeating patterns, to represent different saved values. Assuming a clocked repeating finite pattern, each pattern will repeat themselves after a finite number of clock pulses N, having N different phases. The values saved will be represented by both a pattern, and the phase of the pattern...
This paper introduces a multiple valued counter, based on recharged semi floating gate structures. The counter starts at a sampled voltage, and counts from there, using an input clock signal as an input. Depending on the sampled value and the phase of the input clock signal - the counter can count both up and down. The counting steps can be varied adjusting the input clock amplitude, which in combination...
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