Search results for: Yingtao Jiang

Items from 1 to 20 out of 118 results

article

Effectiveness of HT-assisted sinkhole and blackhole denial of service attacks targeting mesh networks-on-chip

Li Zhang, Xiaohang Wang, Yingtao Jiang, Mei Yang, more

Journal of Systems Architecture > 2018 > 89 > C > 84-94

There are ample opportunities at both design and manufacturing phases to meddle in a many-core chip system, especially its underlining communication fabric, known as the networks-on-chip (NoC), through the inclusion of malicious hardware Trojans (HT). In this paper, we focus on studying two specific HT-assisted Denial-of-Service (DoS) attacks, namely the sinkhole and blackhole attacks, that directly...

article

An Adaptive PAM-4 Analog Equalizer With Boosting-State Detection in the Time Domain

Shunbin Li, Yingtao Jiang, Peng Liu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems > 2017 > 25 > 10 > 2907 - 2916

This paper introduces an improved adaptive analog equalizer that is required in high speed serial receivers using four-level pulse amplitude modulation signaling. By performing boosting-state detection in the time domain, the proposed adaptive analog equalizer can effectively overcome a serious problem that the received signal’s eye-opening tends to be compromised by the convergence accuracy of the...

article

HRC: A 3D NoC Architecture with Genuine Support for Runtime Thermal-Aware Task Management

Xiaohang Wang, Yingtao Jiang, Mei Yang, Hong Li, more

IEEE Transactions on Computers > 2017 > 66 > 10 > 1676 - 1688

In spite of escalating thermal challenges imposed by high power consumption, most reported 3D Network-on-chip (NoC) systems that adopt classic 3D cube (mesh) topology are unable to tackle the thermal management issues directly at the architectural level. Rather, to avoid chip being overheated, tasks running in a “hot” node have to be migrated to a “cooler” one, resulting in increased distance between...

chapter

A Scalable Parameterized NoC Emulator Built Upon Xilinx Virtex-7 FPGA

Ming Zhu, Yingtao Jiang, Mei Yang, Louie De Luna

2017 25th International Conference on Systems Engineering (ICSEng) > 287 - 290

2017 25th International Conference on Systems Engineering (ICSEng)

A number of critical design decisions, such as network topology, buffer sizes, flow control mechanism and so on so forth, have to be evaluated in any NoC the design. Designs and verifications of NoCs are based on either software simulations, which are extremely slow and inaccurate for complex models, or hardware emulations using low/mid-class FPGAs, where the scalability of the NoC system is intensively...

chapter

Building temperature-insensitive nanoscale CMOS circuits with adaptive voltage power supplies

Ming Zhu, Yingtao Jiang, Mei Yang, Xiaohang Wang

2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE) > 1 - 4

2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE)

Temperature variations caused by heat generation and dissipation can have significant performance implications on nanoscale CMOS logic circuits. In this paper, we show that such temperature-induced delay variations can be well controlled or even reduced by dynamically adjusting the voltage level of power supplies over a relatively small range. We thus propose a self-adaptive, temperature-aware voltage...

chapter

On a cyberinfrastructure platform for multidisciplinary, data-intensive scientific research

Xiangrong Ma, Zhao Fu, Yingtao Jiang, Mei Yang, more

2017 IEEE 7th Annual Computing and Communication Workshop and Conference (CCWC) > 1 - 6

2017 IEEE 7th Annual Computing and Communication Workshop and Conference (CCWC)

Development of a cyberinfrastructure (CI) was envisioned to support a large research team geographically spread across the state of Nevada and elsewhere to conduct truly multidisciplinary research in the areas of solar energy, water and environment as well as many related social and economic activities. Although constrained by financial and human resources available, this cyberinfrastructure, named...

article

Half baud-rate, low BER PAM-4 CDR based on SS-MMSE algorithm

Peng Liu, Jun Guo, Yingtao Jiang

Electronics Letters > 2016 > 52 > 25 > 2036 - 2038

A hardware-efficient four-level pulse amplitude modulation (PAM-4) clock and data recovery (CDR) circuit for high speed serial links is proposed, following a sign-sign minimum mean square error (SS-MMSE) algorithm. Using a specially designed continuous-sampling slope detector and a dual-stage digital filter, the proposed SS-MMSE CDR can align the clock phase well with the maximum vertical eye opening,...

article

Data-classification-based SNR estimation for linearly modulated signals

Taleb Moazzeni, Yingtao Jiang, Tian-Ding Chen

Computers & Electrical Engineering > 2016 > 56 > C > 85-95

We present a new numerical approach to SNR estimation of linearly modulated signals after passing through a complex additive white Gaussian noise (AWGN) channel. This classified data (CD) based SNR estimator is particularly suitable for both constant and non-constant modulus constellations, including BPSK, M-PSK and M-QAM. In essence, the received data will be first classified into a number of classes,...

chapter

Handover Cost Optimization in Traffic Management for Multi-homed Mobile Networks

Shupeng Wang, Jianping Wang, Mei Yang, Xiaochun Yun, more

Lecture Notes in Computer Science > Ubiquitous Intelligence and Computing > Ad-Hoc and Intelligent Networks > 295-308

In this paper, we study the traffic management problem for multi-homed mobile networks with the objective of minimizing the overall handover cost. Two different traffic distribution modes are considered in our study: the Fractional Flow Assignment (FFA) mode which assumes the bandwidth demand from one connection is infinitely splittable and can be assigned to different wireless access networks, and...

article

A pareto-optimal runtime power budgeting scheme for many-core systems

Xiaohang Wang, Baoxin Zhao, Ling Wang, Terrence Mak, more

Microprocessors and Microsystems > 2016 > 46 > PB > 136-148

Due to the ever-escalating power consumption, a significant proportion of the future many-core chips is mandatory to be switched off to meet the power budgets. This trend has brought up a paradigm shift from conventional low-power to power budgeting designs, where performance optimization needs to be performed under a tight power budget constraint. There are two key issues to be considered when moving...

article

Ultrasensitive strain gauge with tunable temperature coefficient of resistivity

Lizhi Yi, Weihong Jiao, Changming Zhu, Ke Wu, more

Nano Research > 2016 > 9 > 5 > 1346-1357

We demonstrate an ultrasensitive strain gauge based on a discontinuous metal film with a record detection limit as low as 8.3 × 10^–6. Constructed by well-tunable crevices on the nanometer scale within the film, this gauge exhibits an ultrafast dynamic response to vibrations with a frequency range of 1 Hz to 10 kHz. More importantly, the temperature coefficient of resistivity (TCR) of the metal film...

article

On Fine-Grained Runtime Power Budgeting for Networks-on-Chip Systems

Xiaohang Wang, Baoxin Zhao, Terrence Mak, Mei Yang, more

IEEE Transactions on Computers > 2016 > 65 > 9 > 2780 - 2793

Power budgeting is an essential aspect of networks-on-chip (NoC) to meet the power constraint for on-chip communications while assuring the best possible overall system performance. For simplicity and ease of implementation, existing NoC power budgeting schemes treat all the individual routers uniformly when allocating power to them. However, such homogeneous power budgeting schemes ignore the fact...

chapter

On fully reconfigurable optical torus-based networks-on-chip architecture

Lei Zhang, Mei Yang, Yingtao Jiang, Jianyi Yang, more

2016 IEEE Optical Interconnects Conference (OI) > 82 - 83

2016 IEEE Optical Interconnects Conference (OI)

We propose a fully reconfigurable torus-based Optical NoC architecture: Ouroboros network. It has two reconfiguration modes: 1) arbitrarily change the nodes connection order, 2) split the network into any set of subnetworks and reorder each of them. The reconfiguration is achieved by tuning Micro-Ring Resonators.

chapter

Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip

Xiaohang Wang, Maurizio Palesi, Mei Yang, Yingtao Jiang, more

Lecture Notes in Computer Science > Network and Parallel Computing > Session 6: Best Paper – 1 > 232-247

3-D Networks-on-Chip (NoCs) emerge as a powerful solution to address both the interconnection and design complexity problems facing future Systems-on-Chip (SoCs). Effective run-time application mapping on a 3-D NoC-based Multiprocessor Systems-on-Chip (MPSoC) can be quite challenging, largely due to the fact that the arrival order and task graphs of the target applications are not known a priori....

chapter

On a Chaotic Neural Network with Decaying Chaotic Noise

Tianyi Ma, Ling Wang, Yingtao Jiang, Xiaozong Yang

Lecture Notes in Computer Science > Advances in Neural Networks – ISNN 2005 > Model Design > 497-502

In this paper, we propose a novel chaotic Hopfield neural network (CHNN), which introduces chaotic noise to each neuron of a discrete-time Hopfield neural network (HNN), and the noise is gradually reduced to zero. The proposed CHNN has richer and more complex dynamics than HNN, and the transient chaos enables the network to escape from local energy minima and to settle down at the global optimal solution...

article

An energy-efficient scheduling scheme for time-constrained tasks in local mobile clouds

Ting Shi, Mei Yang, Xiang Li, Qing Lei, more

Pervasive and Mobile Computing > 2016 > 27 > C > 90-105

Mobile Cloud Computing (MCC) enables mobile devices to use resource providers other than mobile devices themselves to host the execution of mobile applications. Various mobile cloud architectures and scheduling algorithms have been studied recently. However, how to utilize MCC to enable mobile devices to run complex real-time applications while keeping high energy efficiency remains a challenge. In...

article

PSS4: Four-Phase Shifted Sinusoid Symbol Signaling for High Speed I/O interconnects

Kejun Wu, Peng Liu, Weidong Wang, Qiaoyan Yu, more

Computers & Electrical Engineering > 2016 > 51 > C > 104-117

Various signaling techniques have been considered for I/O interconnects at 25 Gb/s or higher. However, they either suffer from high baud rate, as in the case of NRZ, or an excess signal-to-noise ratio penalty, as in the case of PAM-4. To overcome these problems, a four-phase shifted sinusoid symbol (PSS-4) signaling method is proposed that can be readily applied to high-speed I/O transceivers. By...

chapter

Load-Similar Node Distribution for Prolonging Network Lifetime in PMRC-Based Wireless Sensor Networks

Qiaoqin Li, Mei Yang, Yan Jin, Jun Zheng, more

Communications in Computer and Information Science > Communication and Networking > 384-393

In this paper, the energy hole problem in Progressive Multi-hop Rotational Clustered (PMRC)-based wireless sensor networks (WSNs) is studied. We first analyze the traffic load distribution in PMRC-based WSNs. Based on the analysis, we propose a novel load-similar node distribution strategy combined with the Minimum Overlapping Layers (MOL) scheme to solve the energy hole problem in PMRC-based WSNs...

chapter

A 20 GHz high speed, low jitter, high accuracy and wide correction range duty cycle corrector

Jun Guo, Peng Liu, Weidong Wang, Jicheng Chen, more

2015 28th IEEE International System-on-Chip Conference (SOCC) > 19 - 24

2015 28th IEEE International System-on-Chip Conference (SOCC)

Duty-cycle correctors (DCCs) are employed in most high-speed VLSI systems to calibrate the clock duty-cycle at 50% to reduce the deterministic jitter introduced by duty-cycle distortion. An all-analogue feedback DCC circuitry with high working frequency, low jitter, high accuracy, and wide correction range is proposed in this paper. A common mode voltage adjuster and an active feedback amplifier are...

chapter

Real-time VLSI architecture for palm rejection using Wronskian Determinant

Abu M Baker, Yingtao Jiang

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) > 1 - 4

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

Several Human Interface Technology applications require reliable palm rejection. Palm rejection in upcoming touch or Pad technology has a need of hardware implementation with requirements of low power and small area. This paper introduces a hardware implementation of a real-time palm rejection based on Wronskian Determinant. This detection algorithm offers regularity, low complexity and accuracy as...

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English (115)
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Keywords

NETWORK-ON-CHIP (13)
NETWORK ROUTING (10)
ROUTING (10)
WIRELESS SENSOR NETWORKS (7)
INTEGRATED CIRCUIT LAYOUT (6)
NETWORK TOPOLOGY (6)
ENERGY CONSUMPTION (5)
MICRO-RING RESONATOR (5)
ANALOG INTEGRATED CIRCUITS (4)
ANALOGUE INTEGRATED CIRCUITS (4)
BANDWIDTH (4)
FIELD PROGRAMMABLE GATE ARRAYS (4)
OPTICAL SWITCHES (4)
POWER DEMAND (4)
SCHEDULING (4)
SIMULATED ANNEALING (4)
TEMPERATURE MEASUREMENT (4)
TEMPERATURE SENSORS (4)
THROUGHPUT (4)
ADAPTIVE SYSTEMS (3)
ALGORITHM DESIGN AND ANALYSIS (3)
BENCHMARK TESTING (3)
CALIBRATION (3)
CHANNEL ALLOCATION (3)
DECIMAL (3)
DYNAMIC PROGRAMMING (3)
ENERGY EFFICIENCY (3)
ESTIMATION (3)
FLOW MEASUREMENT (3)
GRAPH THEORY (3)
LOGIC DESIGN (3)
LOGIC GATES (3)
MANY-CORE (3)
MULTICAST (3)
MULTIPLICATION (3)
NAUKI TECHNICZNE (3)
NETWORK-ON-CHIP (NOC) (3)
NOC (3)
NP-COMPLETE PROBLEM (3)
OPTICAL INTERCONNECTIONS (3)
OPTIMIZATION (3)
PROBABILITY (3)
SYSTEM-ON-CHIP (3)
TILES (3)
TOPOLOGY (3)
8421 BCD (2)
ACCURACY (2)
AD HOC NETWORKS (2)
AD-HOC NETWORK (2)
ADAPTATION MODEL (2)
ADAPTIVE FILTERING APPROACH (2)
ADAPTIVE FILTERS (2)
ANALOG CIRCUITS (2)
ANALOG INTEGRATED CIRCUITS (ICS) (2)
ARCHITECTURE (2)
BANDWIDTH RESOURCE (2)
CHANNEL COORDINATION (2)
CIRCUIT OPTIMISATION (2)
CLOCKS (2)
CLOUD COMPUTING (2)
COMPUTATIONAL COMPLEXITY (2)
COMPUTER ARCHITECTURE (2)
COOLANTS (2)
CORRELATION (2)
CORRELATION METHODS (2)
DATA ACQUISITION (2)
DELAY (2)
DELAY ESTIMATION (2)
DETECTORS (2)
DPCM CODING (2)
ELECTRON TUNNELING (2)
ELECTRONIC MAIL (2)
FLOW CONTROL (2)
FLUID FLOW MEASUREMENT (2)
FPGA (2)
GENETIC ALGORITHM (2)
GEOGRAPHICAL LOCATION (2)
HEURISTIC ALGORITHMS (2)
ID-BASED CRYPTOGRAPHY (2)
IMAGE RECONSTRUCTION (2)
INSERTION LOSS (2)
LIQUID METALS (2)
LOW POWER (2)
LOW SPEED COMMUNICATION CHANNELS (2)
MATHEMATICAL MODEL (2)
MEDICAL IMAGE DATA (2)
MEDICAL IMAGE PROCESSING (2)
MEDICAL IMAGE TRANSMISSION (2)
MESSAGE-DEPENDENT DEADLOCK (2)
MOBILE CLOUD COMPUTING (2)
MOBILE RADIO (2)
MULTICAST COMMUNICATION (2)
MULTIHOP COMMUNICATION (2)
MULTILAYER PERCEPTRON (2)
MULTIPLE SUPPLY VOLTAGES (2)
MULTIPROCESSOR INTERCONNECTION NETWORKS (2)
NETWORK LIFETIME (2)
NETWORKS-ON-CHIP (2)
NONUNIFORM SCALAR QUANTIZATION (2)
OFFLOADING (2)
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Springer (7)
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INFONA - science communication portal

Search results for: Yingtao Jiang

Effectiveness of HT-assisted sinkhole and blackhole denial of service attacks targeting mesh networks-on-chip

An Adaptive PAM-4 Analog Equalizer With Boosting-State Detection in the Time Domain

HRC: A 3D NoC Architecture with Genuine Support for Runtime Thermal-Aware Task Management

A Scalable Parameterized NoC Emulator Built Upon Xilinx Virtex-7 FPGA

Building temperature-insensitive nanoscale CMOS circuits with adaptive voltage power supplies

On a cyberinfrastructure platform for multidisciplinary, data-intensive scientific research

Half baud-rate, low BER PAM-4 CDR based on SS-MMSE algorithm

Data-classification-based SNR estimation for linearly modulated signals

Handover Cost Optimization in Traffic Management for Multi-homed Mobile Networks

A pareto-optimal runtime power budgeting scheme for many-core systems

Ultrasensitive strain gauge with tunable temperature coefficient of resistivity

On Fine-Grained Runtime Power Budgeting for Networks-on-Chip Systems

On fully reconfigurable optical torus-based networks-on-chip architecture

Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip

On a Chaotic Neural Network with Decaying Chaotic Noise

An energy-efficient scheduling scheme for time-constrained tasks in local mobile clouds

PSS4: Four-Phase Shifted Sinusoid Symbol Signaling for High Speed I/O interconnects

Load-Similar Node Distribution for Prolonging Network Lifetime in PMRC-Based Wireless Sensor Networks

A 20 GHz high speed, low jitter, high accuracy and wide correction range duty cycle corrector

Real-time VLSI architecture for palm rejection using Wronskian Determinant

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