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Summary form only given. The demand for multi-faceted wireless applications has led to increased levels of device integration and migration of RF to CMOS technologies. However, the resulting circuits are increasingly susceptible to manufacturing process variations, coupled noise (substrate, power planes) from onchip digital signal processing circuitry, thermal fluctuations (Vt sensitivity to temperature),...
This paper proposes a self-calibrating approach for embedded RF down-conversion mixers. In the proposed approach, the output of the RF mixer is analyzed by using on-chip resources for testing and the mixer performs self-compensation for parametric defects using tuning knobs. The tuning knobs enable the RF mixer to self-calibrate for multi-parameter variations induced due to process variability. Using...
Design and test of high-speed mixed-signal/RF circuits and systems is undergoing a transformation due to the effects of process variations stemming from the use of scaled CMOS technologies that result in significant yield loss. To this effect, post-manufacture tuning for yield recovery is now a necessity for many high-speed electronic circuits and systems and is typically driven by iterative test-and-tune...
CMOS technology scaling along with the resulting large variability of circuit performance has made post-silicon circuit and algorithmic level built-in test and adaptation/tuning almost a necessity for deeply scaled technologies. Currently, circuits are designed to tolerate worst-case process corners. In addition, circuits as well as demodulation/signal processing algorithms must be designed for worst...
As technology scales below the 45 nm CMOS technology node, RF front ends and baseband processors will need to be aggressively over designed to work reliably under worst case channel (environment) conditions as well as worst case manufacturing variations. In this paper, a new dual feedback based design approach is proposed that allows the baseband unit of a wireless OFDM system to adapt dynamically...
Soft errors due to alpha particles, neutrons and environmental noise are of serious concern in highly scaled CMOS circuits. This mandates the use of error/noise tolerance mechanisms in circuit design. Prior work has addressed error correction and compensation techniques for linear digital systems using checksum codes. However no low-cost checksum based technique is found in the literature for nonlinear...
Nanometer circuits are becoming increasingly susceptible to soft errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add soft-error tolerance estimation and optimization to the design flow to handle the increasing susceptibility. The first part of this paper presents...
To address growing production test costs, a low-cost built-in test solution for RF circuits is proposed that is robust to process, supply voltage and temperature variations (PVT variations). The test solution consists of measuring the envelope of the output response to a two-tone test stimulus. This is a relatively low frequency signal compared to the nominal frequency of the RF device under test...
Shallow trench isolation schemes using a LOCOS edge to avoid sharp corner effects are applied to 0.25 /spl mu/m and 0.18 /spl mu/m technologies. Two variations are studied. In the first case (Case A) a mini-LOCOS is grown and deglazed prior to trench etch whereas in the second case (Case B) the deglaze is omitted. Excellent narrow width effect is demonstrated. The V/sub T/ increases by /spl les/50...
Process/device synthesis using automated optimized device design with a set of target/constraint values is investigated to reduce device design time and product cycle time. As a first step, the authors report results on (a) transistor design methodology, (b) TCAD simulator tuning methodology, and (c) device optimization using process sensitivity considerations and a new transistor figure-of-merit...
The simple approach of thermal oxide capped poly refill trench isolation (Rung et al., 1982) is studied with regard to the impact of cap oxide thickness, trench wall thermal oxide thickness, and trench depth on MOSFET and isolation characteristics. It is shown that an increase of cap oxide thickness (t/sub ox/) from 600 to 2000 AA eliminates subthreshold double-hump phenomena, improves isolation V/sub...
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