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This letter provides channel-stress behavior results induced by a local strain technique which consists of the process combination of a damascene-gate and top-cut tensile stress SiN liner for narrow channel-width nFETs using 3-D stress simulations and demonstrations. The dummy-gate removal, which is an intrinsic step in the damascene-gate process, is found to enhance tensile channel stress along the...
Mobility and velocity enhancements of hole on Si (110) and (100) substrates are accurately investigated for short-channel highly-strained pFETs. Local channel stress in short gate length is successfully observed for damascene gate pFETs with stressors by UV-Raman spectroscopy. A high channel stress of -2.4 GPa is measured for a 30-nm gate length device. Hole mobility and saturation velocity are precisely...
Electron mobility enhancement using a top-cut stress liner and the replacement gate process is demonstrated and the concept of stress localization is proposed, for the first time. Eliminating a dummy gate after tensile stress liner formation enhances lateral stress at the channel region and achieves good mobility improvement. A detailed analysis using stress and mobility calculation based on a band...
The stress effect at the channel region of pFETs with compressive stress liner (c-SL) and eSiGe using replacement gate technology is firstly investigated in detail based on the combination of UV-Raman spectroscopy and 3D stress simulation. The gate length effect for the channel stress is confirmed by measurement and simulation. Moreover, the Ion dependence on the channel width is also investigated...
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