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We applied flash lamp annealing (FLA) in Ni-silicidation to our developed dopant confinement layer (DCL) structure for the first time. DCL technique is a novel stress memorization technique (SMT). We successfully improved the short channel effect (SCE) with keeping a high drive current by FLA in Ni-silicidation. For pMOSFET, 2 layers Ni fully-silicide (Ni-FUSI) was selectively formed on gates, and...
Direct comparison between competitive process flows showed that the eSiGe-S/D-last flow is the most promising CMOS integration process for manufacturing 45-nm technology node and beyond because it has good extensibility with various performance boosters, has fewer process steps and suppresses electrical fluctuations. The eSiGe-S/D-last (after offset spacer + I.I.) flow creates a sufficient process...
We fabricated sub-30-nm fully silicide (FUSI) CMOS transistors by a simple method without additional chemical-mechanical-polish and gate-capping-layer processes. The FUSI draped with source/drain (S/D) capping layer (D-FUSI) featuring shallow S/D Ni silicided layer without modulation of geometric structures is suitable to improve electrical characteristics of the short-channel transistor. Drive currents...
We describe the integration of a 45-nm node CMOS for low operation power (LOP) application. The SD extension profile along with a strain channel and a thin-gate-SiON were optimized to keep high drive current at the 45-nm node. A novel STI structure was developed to reduce the SRAM cell size. Nano-clustering silica (NCS) without a middle-etch stopper (MES) was also developed to decrease the wire capacitance...
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