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Low frequency noise characterization is used to compare the quality and reliability of gate dielectric processed using both gate-first and gate-last or replacement metal gate integration schemes. The influence of different processing treatments will be studied, for both planar and FinFET devices, and the obtained results compared with the LF noise specifications of the International Technology Roadmap...
The low-frequency noise of gate-last pMOSFETs is studied, with particular attention to the passivation of oxide traps by fluorine. It is shown that the lowest flicker noise power spectral density is obtained after 6 min of exposure to an SF6 plasma. At the same time, the dominant 1/f-noise mechanism changes from carrier number fluctuations to mobility fluctuations, indicating the de-activation of...
We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by...
A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only...
Abstract MoON has been reported to be a good PMOS candidate. In this paper, we report tuning of the MoON PMOS metal towards Si conduction band-edge with Vtau as low as 0.35V for SiON capped with DyO, using a standard high temperature gate first process flow. Consistent shifts of 450 mV in VFB and Vtau are observed by capping SiON with DyO for MoON gate. Gate leakage as low as 10-7 A/cm2 at 17.6A EOT...
We report band-edge pFET threshold voltage (Vt ~ 0.28 V) for MoOxNy on HfSiON gate dielectric using a standard high temperature gate first metal-inserted poly-stack (MIPS) process flow. We also report p-FETs Vt of 0.45 V using a MoO x/SiON gate stack, meeting the requirement for 45nm high-V t CMOS technology. 30 % improvement in performance compared to our base-line poly-Si/SiON was observed by using...
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