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Modern system-on-a-chip SOC contains hierarchical cores that have multiple levels of design hierarchy. An efficient wrapper design for hierarchical cores is necessary to facilitate modular testing of SOC. In most of the prior work on wrapper design for embedded cores, all the cores are assumed to have a flattened hierarchy, it's not suitable for real-life SOCs. In this paper, a generic IEEE 1500-compliant...
With the increase in complexity of VLSI and the test cost of automatic test equipment (ATE), logic built-in self-test (BIST) has been widely applied. In order to reduce the test time of logic BIST, logic BIST with multiple scan chains has been proposed. However, the main shortcoming of logic BIST with multiple scan chains is low fault coverage (FC). A novel two-dimensional cellular automata (2-DCA),...
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