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Multi-site testing is generally regarded as the most-effective way to reduce the cost of test. Testing two devices on an ATE at the same time is half the cost of testing only one, but only if the ATE does not need twice as many channels. It is general practice in industry to use reduced pin-count test (RPCT) access to facilitate testing more ICs in parallel, as well as testing high pin-count ICs on...
Pipeline defects, which cause emitter-collector shorts, have been quite well known in bipolar processes. Such defects have been, however, rarely reported in CMOS processes. In our recent implementation of the new submicron CMOS26 process in which SWAMI isolation was used, pipeline defects in n-channel FET's were discovered. The pipelines were caused by enhanced phosphorus diffusion along dislocation...
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