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In this paper an improvement over the control structure of the processor architecture reported in is proposed. Each processor in the array was controlled by the central control unit which proved to have some setbacks. These are: 1) the complexity of the control logic which tends to be more complicated as the number of processors gets higher; 2) the necessity to redesign the control logic for any change...
A cellular neural network (CNN) emulator architecture processing real-time video signals is proposed and implemented on FPGA. The main features of this architecture are: 1) No external memory is required; 2) Computation of each pixel is carried out in three clock cycles and; 3) The number of Euler iterations required for the computation of the output values is determined by the number of implemented...
A new processor architecture implementing the Discrete Time Cellular Neural Networks (DT-CNN) on FPGA is proposed. This architecture intends to process video images real time with 3times3 CNN templates and without the use of an external memory. The absence of the external memory decreases the cost and complexity of the system. The architecture is based on a single pipelined cell which is employed...
Cellular nonlinear/neural networks (CNN's) are one of the analog systems that is hard to emulate or simulate on digital systems. It is known that CNN systems are linear for Gabor-type spatial filters. Although it is possible to represent the state equations of the discrete CNN in matrix notation, it is almost impossible to implement the huge state matrix on a digital system without optimization. In...
This paper presents a sufficient condition for the existence, uniqueness and global robust asymptotic stability of the equilibrium point for bidirectional associative memory (BAM) neural networks with discrete time delays. Some numerical examples are given to compare our results with the previous robust stability results derived in the literature.
A field programmable gate array (FPGA) implementation of the Gabor-type filter is presented. The implementation uses the forward Euler approximation with optimal step size to solve the CNN cell-state equation. The FPGA is implemented on Xilinx Spartan XC3S400 device using 219 slices. An image of dimension 60 times 60 can be processed without using any external RAM only with the block RAM.
This paper presents new sufficient conditions for the existence of stable equilibrium points in the total saturation region for delayed cellular neural networks (DCNNs). The obtained results are compared with the previous results derived in the literature. It is also shown that the results of this paper generalize the previous literature results for the existence of stable equilibrium points for DCNNs...
It is shown that the application of Jacobi iteration to the linear algebraic equations obtained from the state equations of a linear CNN with constant input by setting the derivatives of the states to zero yields the steady-state solution of the state equations. It is proved that the Jacobi iteration equation and that obtained by setting the integration time-step to a00-1 in the discrete-time state...
A new state-variable structure with minimum number of multipliers is introduced. It is obtained by the application of the bilinear transformation to the direct form structure. It is also shown that the roundoff-noise gain is invariant under LP-LP transformation for the new structure.<<ETX>>
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