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With rapid technology scaling, the proportion of the static power catches up with dynamic power gradually. To decrease leakage power is becoming more and more important in low-power design. This paper investigates leakage reduction of adiabatic circuits using power-gating schemes under deep submicron process. The energy dissipations of DTGAL (dual transmission gate adiabatic logic) circuits with power-gating...
This paper presents an adiabatic tree multiplier based on modified Booth algorithm, which operates in a single-phase power-clock. All circuits are realized using improved CAL (clocked adiabatic logic) circuits with TSMC 0.18 mum CMOS process. The proposed single-phase adiabatic booth encoder attains energy savings of 82% at 50 MHz and 70% at 300 MHz, compared with its CMOS counterpart. The single-phase...
This paper presents a power-gating scheme for CAL (clocked adiabatic logic) circuits to reduce energy loss during idle state. A transmission gate is used as the power-gating switch. It is inserted between the single-phase power-clock and virtual power-clocks to detach power-gated CAL logic blocks during idle periods. The 8-bit full adders based on the CAL circuits are used to verify the proposed power-gating...
In this paper, the design of pre-settable adiabatic flip-flops and sequential circuits based on the two-phase CPAL (complementary pass-transistor adiabatic logic) is presented. The two-phase CPAL is more suitable for the design of flip-flops and sequential circuits, as it uses fewer transistors than the conventional CMOS implementation and the other adiabatic logic circuits. Pre-settable adiabatic...
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