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Any signal processing architecture has a multiplier as its pillar. Its computational capabilities depend on the multiplier's performance. Also, low-power designs are the need of next generation processors. Reversible logic is one of the promising future low power technologies. High-speed multiplication can be achieved if the carry-propagation is faster. Digital compressors have less latency in carry-propagation...
Monitoring ports, harbors and oceanic territories is gaining huge interest especially to combat military crisis, smuggling and terrorist activities. Underwater Wireless Sensor Network can be a viable solution for tracking objects like trespassing ships approaching a harbor and monitoring the activities on the ocean surfaces. In this paper we have proposed a new paradigm for underwater tracking mechanism.
Power dissipation has become the major concern for circuit design and implementation. Reversible Logic is the best alternative to Irreversible Logic in terms of low power consumption. Circuits designed using reversible logic have a wide array of applications. The Quantum Cost, Garbage Outputs, Ancillary Inputs and Delay are some of the parameters of reversible circuits that can be used to determine...
Reversible logic has emerged as a possible low cost alternative to conventional logic in terms of speed, power consumption and computing capability. An adder block is a very basic and essential component for any processor and optimized design of these adders' results in efficient processors. In this work we propose optimized Binary adders and BCD adders. The adders designed in this work are optimized...
Memory is the fundamental building block of any digital system. Most of the portable devices used today incorporate SRAM arrays which are vital memory elements. The significant role of reversible logic in designing such circuits is to reduce or completely eliminate power dissipation. According to survey, only few design methodologies have been proposed for the SRAM array and to the best of our knowledge,...
Asynchronous systems are designed without any global clock signal. Here computation is achieved by a series of events represented by signal transition edges; hence the speed of computation is determined by the signal propagation delay of the asynchronous circuit and not on the global clock. Some notable problems in synchronous circuit design due to higher performance demand are clock skew, power dissipation...
With growing internet using demands, the need of services at various scales of Quality of Service (QoS) has made appropriate classification of these types of services mandatory. Therefore, the Differentiated Services Architecture has been proposed for service differentiation at various scales of services. DiffServ network is based on traffic classification mechanism. To measure the measurement of...
Here i have reviewed the previous works in literature for low power at gate level logic transformation in synthesis process. I applied the probabilistic power analysis technique with an example f = b(a+c) and same is proved using MATLAB 7.10.0 (R2010a). I showed the advantage of Binary Decision Diagram (BDD) for computing the probability of given Boolean function. The effect of technology mapping...
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