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A novel digital background calibration technique is presented which is applied to high resolution high speed pipelined ADC. This technique is based on the structure of 2.5-bit/stage switched-capacitor multiplying-digital-to-analog converter (MDAC). Several random arrays adopted to carry the error information are introduced in the first two MDACs. Signal correlation theory is used to pick up the error...
This paper is concerned with the design of a high speed current steering DAC. Techniques to improve static precision are preserved while their negative influences on dynamic performance are suppressed. The prototype is implemented with the SMIC 0.13 ??m process. With an update rate of 700 Msamples/s, measurements show that the DAC achieves over 40 dB SFDR under a sampling rate of 700 Ms/s and consumes...
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