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In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported...
We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.
The paper describes the development and the main characteristics of a low-cost Unmanned Underwater Vehicles (UUV) built by the Mechatronics and Dynamic Modelling Laboratory (MDM Lab) of the University of Florence. This vehicle is named FeelHippo, and it is an Autonomous Underwater Vehicle (AUV) purposely developed to participate to the 2013 edition of the Student Autonomous Underwater Vehicle Challenge-Europe...
A. Blaquière: Quelques aspects géométriques des processus optimaux.- C. Castaing: Quelques problèmes de mesurabilité liés à la théorie des commandes.- L. Cesari: Existence theorems for Lagrange and Pontryagin problems of the calculus of variations and optimal control of more-dimensional extensions in Sobolev space.- H. Halkin: Optimal control as programming in infinite dimensional spaces.- C. Olech:...
A new Hardware In the Loop (HIL) architecture to study high speed trains dynamics on full-scale test-rigs is proposed in this work. Through the new architecture different wheel-rail adhesion patterns and, in particular, degraded adhesion conditions can be reproduced on the test-rig. The new strategy will be implemented into the full-scale test-rig of the Railway Research and Approval Center of Firenze-Osmannoro...
In this paper the modelling and control of an innovative Hardware In the Loop (HIL) architecture to test high speed trains on full-scale roller-rigs is described. The new approach allows to reproduce on the roller-rig a generic wheel-rail adhesion pattern and, in particular, degraded adhesion conditions. The presented strategy will be also implemented in the innovative full-scale roller-rig of the...
In the present work the high aspect ratio process (HARP) using a new O3/TEOS based sub atmospheric chemical vapor deposition process was implemented as STI gap fill in sub-65nm CMOS. We prove good gap fill performance up to aspect ratios larger 10:1. Since this fill process doesn't attack the STI liners as compared to HDP, a variety of different STI liners can be implemented
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