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A continuous-time power supply noise monitoring technique features a coverage of voltage domains at Vdd as well as at Vss and multi-channel probing at more than a hundred locations on power planes in a circuit. Methods toward quality on-chip power supply noise measurements are derived. A calibration flow eliminates the offset as well as gain errors among probing channels. A combined evaluation of...
An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 times 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 times 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such...
Logical operations in CMOS digital integration are highly prone to fail as the amount of power-supply (PS) drop approaches to threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, in relation with instruction- level programming for logical failure analysis. Experimental measurements demonstrate that the increased susceptibility...
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