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This paper proposes a dependable dual-port SRAM with 9T/18T bitcell structure. The proposed SRAM has two operating modes: a 9T normal mode and an 18T dependable mode. The 9T bitcell has an outside single-ended bitline as a dedicated read port along with a pair of conventional differential inside bitlines. Therefore, the 18T bitcell has two differential pairs of the outside bitlines and inside bitlines...
A fully integrated 40-Gb/s transmitter and receiver chipset with SFI-5 interface was implemented in a 65-nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides a good jitter performance with a 40-GHz full-rate clock architecture that alleviates pattern-dependent jitter. The measured RMS jitter on the output was 570 to 900 fs at 39.8 Gb/s to 44.6 Gb/s using a 2^31-1...
In this paper, 40 Gb/s SFI-5-compliant TX and RX chips in 65 nm CMOS technology consume 2.8 W each. This low power dissipation allows for a small and low-cost plastic BGA package. The TX has a full-rate clock architecture that is based on a 40 GHz VCO, a 40 Gb/s retiming D-FF, and 40 GHz clock-distribution circuits that lead to a low jitter of 0.57 psrms and 3.1 pspp at 40 Gb/s. A 40/20 GHz clock-timing-adjustment...
A fully integrated 40 Gb/s transmitter and receiver chipset with SFI-5 interface is implemented in a 65 nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides good jitter performance with a 40 GHz full-rate clock architecture that alleviates pattern-dependent jitter and eliminates duty cycle dependence. The measured RMS jitter on the output is 570 fs to 900 fs over...
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