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In order to eliminate the inefficiency of the conventional bus based architecture, network-on-chip (NoC) has been suggested as a novel approach for several years. Considering the trend that hundreds or even thousands of IP blocks will be integrated on a chip, the concept of multi-cluster NoC is proposed. It usually adopts the hybrid architecture mixed with bus based local system and mesh based global...
New tendencies envisage multi-core as a promising solution for embedded application. And the key challenge is how to improve the communication efficiency. In this paper, we propose improved on-chip communication architecture for multi-core embedded system The presented on-chip communication protocol is based on packet connected circuit (PCC), but we improve it to fit different frequency requirements...
Multiprocessor System-on-Chip is a promising solution for the high performance Embedded System. This paper is based on an independent research about Hierarchical NoC (Network-on-chip). By integrating 16 ARM cores in the FPGA board, we can bring out the four-channel fade-in and fade-out for real-time streaming media. We present two parallel models for our multiprocessor. One is fine-grained parallelization,...
We introduce a novel hierarchical cluster based cache coherence scheme for large-scale NoC based distributed memory architectures. We describe the hierarchical memory organization. We show analytically that the proposed scheme has better performance than traditional counterparts both in memory overhead and communication cost.
Besides processors, DSPs and other IP blocks, Network on Chip (NoC) also integrates lots of memories. However, the research of on chip memory subsystem for NoC has not been undertaken thoroughly. In this paper, a distributed None Uniform Memory Access (NUMA) memory architecture for NoC is developed; the performance and the programming mode of this system are discussed. Two kinds of parallel algorithms...
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