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While multi-core architectures, by exploring the thread/process level parallelism, help to lower down the power/thermal barrier for single core architectures, power/thermal issues are still the primary limiting factors to achieve high computing performance. In this paper, we study the problem of how to maximize the computing performance of multi-core platforms without violating their peak temperature...
For multi-core partitioned scheduling problem, bin-packing based techniques (First-Fit, Best-Fit and Worst-Fit) are dominated, through which the utilization of a task modeled as the “size” of the object and the utilization bound of a processor modeled as the “capacity” of the bin. However, any traditional bin-packing techniques can not perfectly represent the characteristics of processors and tasks,...
As IC technology continues to evolve and more transistors are integrated into a single chip, high chip temperature due to high power density not only increases packaging/cooling cost, but also severely degrades reliability and the performance of computing systems. In the meantime, as transistor feature size continues to shrink, it becomes difficult to precisely control the manufacturing process. The...
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