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We present six- and eight-transistor (6T, 8T) FinFET SRAM cell schemes using shorted gate (SG) and low power (LP) FinFET configurations and comprehensively evaluate their leakage currents. FinFETs provide significantly lower leakage current and higher on-current than bulk-CMOS transistors and this allows 8T FinFET SRAM schemes to greatly outperform 8T 32nm CMOS SRAM cells. Reverse-biasing the back...
In this study we present 3T and 3T1D DRAM cells designed using FinFET technology. Overall, the 3T DRAM cell has a 43.6% faster write speed than the 3T1D cell and uses less dynamic current (30.4% less write current and 14.6% less read current). The FinFET 3T1D DRAM cell offers a 16.7% faster read speed and 48.6% less read leakage current than the 3T1D cell. The 3T DRAM cell offers less variation in...
This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder. These schemes differ in front- and back-gate connections and input signal swing. Simulations of these schemes were performed using a 32nm FinFET technology model and the schemes' performance was evaluated in terms of dynamic current consumption, delay, and leakage current consumption...
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