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This paper presents hardware implementations of Taylor series. The focus will be on the exponential function but the methodology is applicable on any unary function. Two different architectures are investigated, one, original, straight forward and one modified structure. The outcomes are higher performance, lower area, and lower power consumption for the modified architecture compared to the original.
In July 2000 the five-year Swedish national “Socware Research & Education Program” was started. One of the aims of the program was to develop an innovative unique educational curriculum in System-on-Chip design. The program was targeted at undergraduate and graduate. In total the program received USD $15 million funding. In 2005 the program entered a new phase; more than 500 Master's students...
This paper presents an analysis of energy dissipation of a decimation filter chain of four Half Band Digital (HBD) filters operated in the sub-threshold (sub-V T ) region with throughput constraints. To combat speed degradation due to scaling of supply voltage, various HBD filters are implemented as unfolded structures. The designs are synthesized in 65nm CMOS technology with low-power and...
This paper presents a methodology to reduce the power consumption, silicon area, as well as increasing the performance, in digital filters that are feasible for wireless communication circuitries. The method is based on arithmetic reductions in a wave digital filter. Basically, the multipliers are removed to reduce the number of arithmetic operations. All parameters including the dynamic and static...
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