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This paper shows a novel methodology to improve unrolled CORDIC architectures. The methodology is based on removing adder stages starting from the first stage. As an example, a 19-stage CORDIC is used but the methodology is applicable on CORDICs with an arbitrary number of stages. The CORDIC is implemented, simulated, and synthesized into hardware. In the paper, the performance is shown to be increased...
This paper presents an area/energy efficient soft-output MIMO detector that supports the detection of spatial-multiplexing (SM), spatial-diversity (SD), and space-division-multiple-access (SDMA) signals. The developed near-optimal detection algorithms for these three modes share most of the mathematical operations to enable extensive hardware reuse. A unified VLSI architecture is accordingly designed...
High performance implementations of unary functions are important in many applications e.g. in the wireless communication area. This paper shows the development and VLSI implementation of unary functions like the logarithmic and exponential function, by using a novel approximation methodology based on parabolic synthesis, which is compared to the well known CORDIC algorithm. Both designs are synthesized...
Computing Euclidean Distances is a very important operation in digital communication, especially in the case of trellis coded modulation, where it is used numerously. This paper shows that a substantial reduction in complexity can be achieved in hardware processing elements for computing Euclidean Distances. A reduction in complexity down to 39% is shown compared to traditional designs. The paper...
This paper shows a novel methodology to reduce the power consumption and complexity in unrolled CORDIC architectures. It is a methodology based on removing adder and subtractor stages starting from the first stage. The stages are replaced with a number of MUXes. Three to four stages can be removed with substantial reduction in complexity and power consumption. The methodology is applicable on CORDICs...
This paper presents an analysis on energy dissipation of digital half-band filters operating in the sub-threshold (sub-VT) region with throughput and supply voltage constraints. A 12-bit filter is implemented along with various unfolded structures, used to form a decimation filter chain. The designs are synthesized in a 65 nm low-leakage CMOS technology with various threshold voltages. A sub-VT energy...
This paper presents an efficient and reconfigurable MIMO detector design solution targeting on the emerging LTEA downlink. The detector supports signal detection of multiple MIMO modes which are spatial-multiplexing (SM), spatial-diversity (SD), and space-division-multiple-access (SDMA). Cost-reduction is achieved by algorithm and architecture co-design where low-complexity, near-maximum-likelihood...
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